Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in the present disclosure and are not admitted to be prior art by inclusion in this section.
In systems for processing data, for example, packet processing systems for processing packets transmitted on a network, some parts of the processing, such as for example bridging decisions (e.g. layer 2), are suitable to be performed by a pipeline processor. Other types of processing, such as for example, routing (e.g., layer 3), identifying previously unknown flows of packets through a network switch and checking that selected packets do not contain malicious content, are performed by a central processing unit (CPU). In order to minimize latency when performing operations using the CPU, data that is needed by the CPU for processing is loaded from an external memory into a cache memory.